March+24nd+2017+by+Michael

Von Neumann: data and programs are indistinguishable and can therefore use the same memory
 * Von Neumann Architecture**

How to describe Von Neumann processor architecture? - **Stored-program concept,** Storage of instructions in computer memory to enable it to perform a variety of tasks in sequence or intermittently. -Instructions and data use the primary memory(in a continuous block) -use of single processor -Follow the sequential set of instructions(instruction are executed in sequence) -program consists of a sequence of stored instruction

speed-cost sequence: speed ++ cost++ off-line storage, hard disk, RAM, cache, CPU Register

Describe what does it meant by register? Temporary storage location inside the (micro) processor

**functions of components** **Processor = ALU + CU + registers**

**ALU:** **Accumulator**: a register inside the ALU. It is a single general-purpose register where all values are held when processed by arithmetic and logical operations.

Do logical and arithmetic operations

**CU:** **Program counter (PC)**: A program counter is a register in a computer processor that contains the address (location) of the instruction being executed at the current time. As each instruction gets fetched, the program counter increases its stored value by 1. After each instruction is fetched, the program counter points to the next instruction in the sequence. When the computer restarts or is reset, the program counter normally reverts to 0.

Current Instruction Register (CIR):Instruction Register is where the instruction bit pattern is loaded for execution. Instruction Decoder is triggered by the instruction bit pattern during execution.

**Register:** (MDR) Used to temporarily store data read from or written to memory. All transfers from memory to the CPU go via the Memory Data Register.

MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR.The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register.Far more complex memory interfaces exist, but this is the least that can work.

**The fetch-decode-execute cycle**

**fetch** The program counter (PC) stores the address of the next instruction to be fetched. Then the contents of the Program Counter are incremented When the next instruction is needed, its address is copied from the PC and placed in the memory address register (MAR) This location, or address, is found and the contents are placed in the memory data register (MDR) The contents of the MDR are then copied to the current instruction register (CIR) The CIR holds the instruction that is about to be executed.

**decode** The instruction in the CIR is split into its individual parts. (operation code and operand) Operation: +, Operand: a, b If the operand is an address, the address is copied to the MAR and the data are fetched and placed in the MDR a and b are addresses The operation is decoded by referring to a lookup table which gives the control unit the instructions about what needs to be done.

**execute** The execute phase depends on the nature of the instruction, e.g., arithmetic, accessing a value (or storing) in main memory

Explain what the accumulator holds and how the contents change during the fetch-execute cycle. -Hold the data currently being processed or(result of calculation is held in accumulator) -before being passed to memory unit

Explain what the program counter(PC) holds and how the content change during the fetch-execute cycle

-The address of the next instruction -Contents incremented -Contents changed by a jump instruction

State what is stored in each of the following special purpose registers in a computer and explain how the contents are altered during the fetch/execute cycle

-Can be changed by contents of PC being copied into it -Can be changed by memory address being copied to it from CIR
 * 1) MAR: -The address in memory of the data/ instruction to be accessed

ii) MDR: -The data/instruction to be used  -Is changed every time an address in MAR is accessed  -Stores data from Accumulator on its way to being stored in memory

iii)CIR: -Stores an instruction  -while it is being decoded/executed/carried out  -Contents change when an instruction from memory has been placed in MDR, and then it is copied from MDR to CIR

(iv)PC: - The address of the next instruction - Content is incremented after the address is read -Content is altered to specific address if instruction is a jump instruction

(v)IR: -Stores an integer value -Which is added to the base address in the instruction -Used for the successive reading of values from memory locations -Can be incremented after use

**Using buses to convey data** **Data bus** Carry data needs to be transferred from one hardware component to another. MDR is at one end of the data bus. The processor has instructions to read values from main memory and store values in memory. ➔ bi-directional

**Control Bus** Send control signals from the control unit to the other components of the system. A separate wire is dedicated to a particular control signal, e.g.:A completed data transfer (r/w) operation Reset button pressed Interrupt request Interrupt acknowledgement

**Address Bus** Carry the address of the main memory location or I/O device which is about to be used. Send address values only in one direction, e.g. from the processor to the MAR

**Parallel processing system**

Parallel processor:

-More than one processor -to perform a single job -Each processor is used to perform a task which is a part of the entire problem

Math co-processor:

-an additional processor which works alongside the main processor -Processor capable of processing large representations/ many bytes // used large size registers -Particularly used for floating point calculations

Array processor:

-Allows a single instruction to be carried out… -simultaneously on a number of data locations // processor has several ALUs -Used to process all the values in an array at the same time